Homepage Dipl.-Ing. Tilo Meister

Dresden University of Technology
Institute of Electromechanical and
Electronic Design

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Dipl.-Ing. Tilo Meister
Scientific Assistant

Research:

Optimization Algorithms for Automatic Pin Assignment

Publications:

Conference Publication (6/2011) SLIP 2011	T. Meister, J. Lienig, G. Thomke, Interface Optimization for Improved Routability in Chip-Package-Board Co-Design Proc. of 13th ACM/IEEE Int. Workshop on System Level Interconnect Prediction (SLIP 2011), San Diego, CA, June 2011. (PDF)
Conference Publication (5/2010) DASS 2010	R. Fischbach, J. Lienig, T. Meister, Herausforderungen bei der Automatisierung des Layoutentwurfs bei dreidimensionalen heterogenen Systemen Tagungsband Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2010), Fraunhofer Verlag, ISBN: 978-3-8396-0126-6, pp. 37-42, Mai 2010.
Conference Publication (5/2010) edaWorkshop 10	T. Meister, J. Lienig, Routability Prediction for Three-Dimensional Circuits Tagungsband edaWorkshop 10, VDE Verlag, ISBN: 978-3-8007-3252-4, pp. 29-34, Mai 2010.
Book Chapter (04/2010)	T. Meister, J. Lienig, G. Thomke, Universal Methodology to Handle Differential Pairs During Pin Assignment VLSI-SoC: Design Methodologies for SoC and SiP, Ch. Piguet, R. Reis , D. Soudris (eds.) Springer Verlag, ISBN 978-3-642-12266-8, pp. 22-42, 2010. (Leseprobe)
Conference Publication (9/2009) ZuE09	T. Meister, J. Lienig, Neue Herausforderungen an die Verdrahtungsvorhersage beim 3D-Layoutentwurf GMM-Fachbericht 61, Zuverlässigkeit und Entwurf, VDE Verlag, pp. 99-106, Sept. 2009. (PDF)
Invited Talk (7/2009) SLIP 2009	R. Fischbach, J. Lienig, T. Meister, From 3D Circuit Technologies and Data Structures to Interconnect Prediction Proc. of 2009 Int. Workshop on System Level Interconnect Prediction (SLIP), San Francisco, CA, pp. 77-84, July 2009. (PDF)
Conference Publication (10/2008) VLSI-SoC 2008	T. Meister, J. Lienig, G. Thomke, Universal Methodology to Handle Differential Pairs During Pin Assignment Proc. of the 16th IFIP/IEEE Int. Conf. on Very Large Scale Integration (VLSI-SoC 2008), Rhodes Island, Greece, pp. 347-352, Oct. 2008, ISBN 978-3-901882-32-6. (PDF)
Conference Publication (04/2008) Analog08	T. Meister, J. Lienig, G. Thomke, Pinzuordnungs-Algorithmen für hochkomplexe Area-Array-Komponenten GMM-Fachbericht ANALOG '08, Siegen, pp. 177-182, April 2008. (PDF)
Conference Publication (03/2008) DATE08	T. Meister, J. Lienig, G. Thomke, Novel Pin Assignment Algorithms for Components with Very High Pin Counts Proceedings Design, Automation and Test in Europe (DATE), Munich, pp. 837-842, March 2008. (PDF)
Diploma Thesis (10/2006) TU Dresden, IBM	Considering Differential Pairs During Automatic Pin Assignment
Internship (5/2006) IBM	Implementation of Pin Assignment Algorithms and Design Analysis Algorithms
Student Research Project (9/2005) TU Dresden, IBM	Pin Assignment Optimization for Complex Printed Circuit Boards

Biography:

10/2001 - 12/2006	Electrical Engineering Student, TU Dresden
Since 1/2007	Scientific assistant, TU Dresden

Contact:

Phone	+49 351 463 3 47 05
Fax	+49 351 463 3 71 83
E-Mail	tilo.meisterifte.de
Letters	TU Dresden
	Institut für Feinwerktechnik und Elektronik-Design
	01062 Dresden, Germany
Parcels/Courier	TU Dresden
	Institut für Feinwerktechnik und Elektronik-Design
	Helmholtzstraße 10
	01069 Dresden, Germany
Visitors	Barkhausenbau
	Helmholtzstraße 18
	Office II/41

Last Update: 15.06.2011