VLSI Physical Design:
From Graph Partitioning to Timing Closure
Andrew B. Kahng, Jens Lienig,
Igor L. Markov, Jin Hu
2011, 310 pages, Springer
978-90-481-9590-9, eBook 978-90-481-9591-6
ifte.de if you find any errors.
p. 16 in Chapter 1: line 1 "as
similar to an FPGA" → "is similar to an FPGA".
p. 61 in Chapter 3, Fig 3: the
slicing trees don't impose any order on the arrangement of the cut lines,
e.g., modules c and d are swapped in the figure. Thus, generating the
floorplan from a slicing tree is ambiguous. For vertical cuts, the left
child should represent the left submodule; for horizontal cuts, the left
child should represent the lower submodule; trees are evaluated in
top-down and left-right manner, and floorplans are generated from
lower-left towards upper-right corner.
p. 124 in Chapter 4: The
legalization of mixed-size netlists that contain large movable blocks is
particularly challenging [4.14] → [4.7].
p. 143, in Chapter 5, Fig
5.14: "Hanan Points" is missing one Hanan point at the top.
p. 186 in Chapter 6: Forbidden
pitch rules prohibit routing wires at certain distances apart, but
allows small or greater spacings → ...but allow smaller or greater
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