Zur Startseite des Instituts für Feinwerktechnik und Elektronik-Design

Dresden University of Technology
Institute of Electromechanical and
Electronic Design

 

Home

Electromechanical Design

Electronic Design

Contract Services

Research

Teaching

Faculty and Staff

Information

 

Dr.-Ing. Johann Knechtel
Former Researcher

German 

 

 

 

Research Interests:

 

VLSI Physical Design Automation for 3D Integration

 

Biography:

 

Johann Knechtel received the M.Sc. in Information Systems Engineering (Dipl.-Ing.) in 2010 and the Ph.D. in Computer Engineering (Dr.-Ing.) in 2014, both from Dresden University of Technology, Germany.

 

Dr. Knechtel is currently a Postdoctoral Associate at the DfX Lab, New York University Abu Dhabi, UAE. From 2010 to 2014, he was a Research Associate and Scholar with the DFG Research Training Group Nano- and Biotechnologies for Packaging of Electronic Systems, and a Ph.D. Student at the Institute of Electromechanical and Electronic Design, Dresden University of Technology. In 2012, he was a Research Assistant with the Dept. of Computer Science and Engineering, Chinese University of Hong Kong, China. In 2010, he was a Visiting Research Student with the Dept. of Electrical Engineering and Computer Science, University of Michigan, USA.

 

His research interests cover VLSI Physical Design Automation with emphasis on 3D Integration.

 

Publications (English only):

  • J. Knechtel, J. Lienig, "Physical Design Automation for 3D Chip Stacks – Challenges and Solutions", in Proc. International Symposium on Physical Design, pp. 33-40, 2016 (PDF)

  • P. Budhathoki, J. Knechtel, A. Henschel, I. A. M. Elfadel, "Integrating 3D Floorplanning and Optimization of Thermal Through-Silicon Vias", in 3D Stacked Chips – From Emerging Processes to Heterogeneous Systems, I. A. M. Elfadel, G. Fettweis (eds.), Springer, ISBN 978-3-319-20480-2, 2016 (Link)

  • J. Knechtel, J. Lienig, C.C.N. Sze, "Challenges and Future Directions of 3D Physical Design", in Physical Design for 3D Integrated Circuits., A. Todri-Sanial, Ch. S. Tan (eds.), CRC Press, ISBN 978-1-498-71036-7, pp. 357-386, 2015 (Link)

  • J. Knechtel, E. F. Y. Young, J. Lienig, "Planning Massive Interconnects in 3D Chips", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(11):1808-1821, 2015 (PDF)

  • J. Knechtel, "Interconnect Planning for Physical Design of 3D Integrated Circuits", PhD dissertation, in Fortschritt-Berichte VDI Reihe 20 Nr. 445, VDI-Verlag Düsseldorf, ISBN 978-3-18-345520-1 ISSN 0178-9473, 2014 (link to hardcopy, citable link to softcopy)

  • J. Knechtel, E. F. Y. Young, J. Lienig, "Structural Planning of 3D-IC Interconnects by Block Alignment", in Proc. Asia South Pacific Design Automation Conference, pp. 53-60, 2014 (PDF)

  • P. Budhathoki, J. Knechtel, A. Henschel, I. Elfadel, "Integration of Thermal Management and Floorplanning Based on Three-Dimensional Layout Representations", in Proc. International Conference on Electronics, Circuits, and Systems, pp. 962-965, 2013 (PDF)

  • R. Fischbach, J. Knechtel, J. Lienig, "Utilizing 2D and 3D Rectilinear Blocks for Efficient IP Reuse and Floorplanning of 3D-Integrated Systems", in Proc. International Symposium on Physical Design, pp. 11-16, 2013 (PDF)

  • J. Knechtel, I. L. Markov, J. Lienig, M. Thiele, "Multiobjective Optimization of Deadspace, a Critical Resource for 3D-IC Integration", in Proc. International Conference on Computer-Aided Design, pp. 705-712, 2012 (PDF)

  • J. Knechtel, I. L. Markov, J. Lienig, "Assembling 2-D Blocks into 3-D Chips", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(2):228-241, 2012 (PDF)

  • R. Fischbach, J. Lienig, J. Knechtel, "Investigating Modern Layout Representations for Improved 3D Design Automation", in Proc. Great Lakes Symposium on VLSI, pp. 337-342, 2011 (PDF)

  • J. Knechtel, I. L. Markov, J. Lienig, "Assembling 2D Blocks into 3D Chips", in Proc. International Symposium on Physical Design, pp. 81-88, 2011 (PDF)

Contact:

 

Phone

+49 351 463 39612

Fax

+49 351 463 37183

E-Mail

johann.knechtelifte.de

Letters

TU Dresden

 

Institut für Feinwerktechnik und Elektronik-Design

 

01062 Dresden

Office

Barkhausenbau

 

Helmholtzstraße 18

 

Room II/47

 

 Impressum

Last update: Feb 22, 2016