A. Kahng, J. Lienig, I. Markov, J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure [Book's webpage] [Springer] [amazon.de] [amazon.com]. Springer-Verlag, Berlin, Heidelberg, New York, ISBN 978-90-481-9590-9, 2011.

J. Lienig, Layoutsynthese elektronischer Schaltungen — Grundlegende Algorithmen für die Entwurfsautomatisierung  (Translation: Physical Design of Electronic Circuits — Basic Algorithms) [more]. Springer-Verlag, Berlin, Heidelberg, New York, ISBN 978-3-540-29627-0, 2006.

J. Lienig, Anwendung evolutionärer Algorithmen für den rechnergestützten Entwurf des Schaltungslayouts (Translation: Evolutionary Algorithms Applied to VLSI Physical Design.) Fortschrittberichte VDI, Reihe 20, Nummer 228. VDI-Verlag, Düsseldorf, ISBN 3-18-322820-3, 1996.

J. Lienig, Ein Verdrahtungssystem für den rechnergestützten Layoutentwurf von Multichipträgern (Translation: Routing Strategies for the Computer-Aided Design of Multi-Chip Modules.) Fortschrittberichte VDI, Reihe 9, Nummer 119. VDI-Verlag, Düsseldorf, ISBN 3-18-141909-5, 1991.

G. Jerke, J. Lienig, J. B. Freuer "Constraint-Driven Design Methodology: A Path to Analog Design Automation," [more] Analog Layout Synthesis — A Survey of Topological Approaches, H. Graeb (ed.) Springer Verlag, New York, ISBN 978-1-4419-6931-6, pp. 271-299, 2011.

T. Meister, J. Lienig, G. Thomke "Universal Methodology to Handle Differential Pairs during Pin Assignment," [more] VLSI-SoC: Design Methodologies for SoC and SiP, Ch. Piguet, R. Reis , D. Soudris (eds.) Springer Verlag, Boston, ISBN 978-3-642-12266-8, pp. 22-42, 2010.

J. P. Cohoon, J. Karro, J. Lienig "Evolutionary Algorithms for the Physical Design of VLSI Circuits," [pdf, ps] Advances in Evolutionary Computing: Theory and Applications, [more] Ghosh, A., Tsutsui, S. (eds.) Springer Verlag, London, ISBN 978-3-540-43330-9, pp. 683-712, 2003.

J. Lienig "Physical Design of VLSI Circuits and the Application of Genetic Algorithms," [pdf, ps] Evolutionary Algorithms in Engineering Applications, [more] Dasgupta, D., Michalewicz, Z. (eds.) Springer Verlag, Berlin, ISBN 978-3-540-62021-1, pp. 277-292, 2001.

W. N. Martin, J. Lienig, J. P. Cohoon "Island (Migration) Models: Evolutionary Algorithms Based on Punctuated Equilibria," [pdf, ps] Handbook of Evolutionary Computation, Oxford University Press, New York, NY, ISBN 978-07-503-0392-7 pp. C6.3:1-C6.3:16, 1997.

J. Knechtel, I. L. Markov, J. Lienig "Assembling 2-D Blocks into 3-D Chips," [pdf] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 228-241, Feb. 2012.

M. Thiele, J. Lienig "Der Feind auf dem Chip — Elektromigration in digitalen Schaltungen," [pdf, elektroniknet.de] Elektronik, Heft 2, pp. 32-36, Feb. 2012.

F. Reifegerste, J. Lienig "Modelling of the Temperature and Current Dependence of LED Spectra," [pdf]  Journal of Light & Visual Environment, vol. 32, no. 3  pp. 288-294, Aug.  2008.

A. Richter, G. Paschew, S. Klatt, J. Lienig, K.-F. Arndt, H.-J. P. Adler "Review on Hydrogel-based pH Sensors and Microsensors," [pdf]  Sensors, vol. 8,  pp. 561-581, Jan.  2008.

A. Richter, W. Krause, J. Lienig, K.-F. Arndt "Polymernetzwerke als Aktor-Sensor-Systeme für die Automatisierung biomedizinischer Geräte (Translation: Polymer Networks as Actor and Sensor Systems to be Used for Automation of Biomedical Devices)," [pdf] Biomedizinische Technik, vol. 50, no. 3, pp. 66-68, March 2005.

G. Jerke, J. Lienig "Hierarchical Current Density Verification in Arbitrarily Shaped Metallization Patterns of Analog Circuits," [pdf, ps] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 1, pp. 80-90, Jan. 2004.

J. Lienig, G. Jerke "Elektromigration — eine neue Herausforderung beim Entwurf elektronischer Baugruppen (Translation: Electromigration — A New Challenge in Electronic Design)," F&M Feinwerktechnik, Mikrotechnik, Mikroelektronik, Part I/Teil I: Ursachen und Beeinflussungsmöglichkeiten [pdf]: pp. 36-39, Oct. 2002, Part II/Teil II: Stromabhängige Verdrahtung von Leiterbahnen [pdf]: pp. 26-28, Jan./Feb. 2003, Part III/Teil III: Berechnung von Stromdichten [pdf]: pp. 12-15, March 2003.

J. Lienig "IC-Layoutentwurf vor neuen Herausforderungen (Translation: IC-Placement and Routing Face New Challenges)," [pdf] F&M Feinwerktechnik, Mikrotechnik, Mikroelektronik, pp. 76-78, Dec. 1999.

J. Lienig "A Parallel Genetic Algorithm for Performance-Driven VLSI Routing," [pdf, ps] IEEE Transactions on Evolutionary Computation, vol. 1, no. 1, pp. 29-39, 1997.

J. Lienig "Evolutionäre Algorithmen für den Layoutentwurf" (Translation: Evolutionary Algorithms for Physical Design Automation), F&M Feinwerktechnik, Mikrotechnik, Mikroelektronik, pp. 406-410, June 1997.

J. Lienig "Anwendung evolutionärer Algorithmen für den rechnergestützten Entwurf des Schaltungslayouts" (Translation: Evolutionary Algorithms Applied to Circuit Design)”, Verbindungstechnik in der Elektronik und Feinwerktechnik, Heft 2 (1997),  pp. 96-97, April 1997.

J. Lienig, K. Thulasiraman "GASBOR: A Genetic Algorithm Approach for Solving the Switchbox Routing Problem," [pdf, ps] Journal of Circuits, Systems, and Computers, World Scientific Publishing Co., Vol. 6, No. 4, pp. 359-373, 1996.

J. Lienig, K. Thulasiraman "A Genetic Algorithm for Channel Routing in VLSI Circuits," [pdf, ps] Evolutionary Computation, MIT Press, Vol. 1, No. 4, pp. 293-311, 1994.

H. Brandt, J. Lienig, G. Röhrs "Ein genetischer Algorithmus zur Optimierung von Verdrahtungsstrukturen" (Translation: A Genetic Algorithm to Optimize Routing Structures)," Wissenschaftliche Zeitschrift der TU Dresden, Heft 2, pp. 93-97, 1992.

J. Lienig "Ein Verdrahtungssystem zum rechnergestützten Layoutentwurf von Multichipträgern" (Translation: A Routing System for the Computer-Aided Design of Special Multi-Chip Modules)," Wissenschaftliche Zeitschrift der TU Dresden, Heft 5/6, pp. 157-161, 1991.

J. Lienig, D. A. Mlynski "Mehrlagenkanalverdrahtung unter Einbeziehung technologischer Randbedingungen" (Translation: Technology-Oriented Multilayer Channel Routing)," Wissenschaftliche Zeitschrift der TU Dresden, Heft 5/6, pp. 163-167, 1991.

A. Krinke, J. Lienig, An Ontology for Constraints in Custom IC Design [pdf] Proc. of the 20th European Conf. on Circuit Theory and Design (ECCTD 2011), Linköping, Sweden, pp. 343-345, Aug. 2011.

T. Meister, J. Lienig, G. Thomke "Interface Optimization for Improved Routability in Chip-Package-Board Co-Design," [pdf] Proc. of 13th ACM/IEEE Int. Workshop on System Level Interconnect Prediction (SLIP 2011), San Diego, CA, pp. 1-8, June 2011.

R. Fischbach, J. Lienig, J. Knechtel "Investigating Modern Layout Representations for Improved 3D Design Automation," [pdf] Proc. of the Great Lakes Symposium on VLSI (GLSVLSI 2011), Lausanne, Switzerland, pp. 337-342, May 2011.

J. Knechtel, I. L. Markov, J. Lienig "Assembling 2D Blocks into 3D Chips," [pdf] Proc. of the Int. Symposium on Physical Design (ISPD'11), Santa Barbara, CA, pp. 81-88, March 2011.

F. Krämer, S. Rzepka, S. Wiese, J. Lienig "Realistic Stress Representation in 2nd Level Interconnections of Productive BGA Components During Drop Test Simulations," [DOI:10.1109/EPTC.2010.5702737] Proc. 12th Electronics Packaging Technology Conf., EPTC, Singapore, pp. 750-756, Dec. 2010.

R. Fischbach, J. Lienig, M. Thiele "Solution Space Investigation and Comparison of Modern Data Structures for Heterogeneous 3D Designs," [DOI:10.1109/3DIC.2010.5751476] Proc. of 2nd IEEE Int. 3D System Integration Conf., 3DIC, Munich, pp. 1-8, Nov. 16-18, 2010.

P. Schneider, A. Heinig, R. Fischbach, J. Lienig, S. Reitz, J. Stolle, A. Wilde "Integration of Multi Physics Modeling of 3D Stacks into Modern 3D Data Structures," [pdf] Proc. of 2nd IEEE Int. 3D System Integration Conf., 3DIC, Munich, pp. 1-6, Nov. 16-18, 2010.

F. Krämer, S. Wiese, S. Rzepka, W. Faust, J. Lienig "A Detailed Investigation of the Failure Formation of Copper Trace Cracks During Drop Tests," [DOI:10.1109/ESTC.2010.5642938] Proc. 3rd Electronics System Integration Technology Conf., ESTC, Berlin, pp. 1-6, Sept. 2010.

F. Krämer, S. Rzepka, S. Wiese, J. Lienig "The Effect of Copper Trace Routing on the Drop Test Reliability of BGA Modules," [pdf] Proc. 60th Electronic Components and Technology Conf., ECTC, Las Vegas, NV, pp. 1217-1225, June 2010.

F. Krämer, S. Wiese, S. Rzepka, J. Lienig "BGA Lifetime Prediction in JEDEC Drop Tests Accounting for Copper Trace Routing Effects," [pdf] Proc. 11th Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE, Bordeaux, pp. 1-8, April 2010.

G. Jerke, J. Lienig "Early-Stage Determination of Current-Density Criticality in Interconnects," [pdf] Proc. of the 11th IEEE Int. International Symposium on Quality Electronic Design (ISQED 2010), San Jose, CA, pp. 667-774, March 2010.

A. Nassaj, J. Lienig, G. Jerke "A New Methodology for Constraint-Driven Layout Design of Analog Circuits," [pdf] Proc. of the 16th IEEE Int. Conference on Electronics, Circuits and Systems (ICECS 2009), Hammamet, Tunisia, pp. 996-999, Dec. 2009.

R. Fischbach, J. Lienig, T. Meister "From 3D Circuit Technologies and Data Structures to Interconnect Prediction," Invited Talk, [pdf] Proc. of 2009 Int. Workshop on System Level Interconnect Prediction (SLIP), San Francisco, CA, pp. 77-84, July 2009.

F. Krämer, S. Rzepka, J. Lienig "Lifetime Modeling for JEDEC Drop Tests," [pdf] Proc. 10th Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE, pp. 309-317, April 2009.

G. Jerke, J. Lienig "Constraint-driven Design — The Next Step Towards Analog Design Automation," Invited Talk, [pdf, slides] Proc. of the Int. Symposium on Physical Design (ISPD'09), San Diego, CA, pp. 75-82, March 2009.

T. Meister, J. Lienig, G. Thomke "Universal Methodology to Handle Differential Pairs During Pin Assignment," [pdf] Proc. of the 16th IFIP/IEEE Int. Conf. on Very Large Scale Integration (VLSI-SoC 2008), Rhodes Island, Greece, pp. 347-352, Oct. 2008.

A. Nassaj, J. Lienig, G. Jerke "A Constraint-driven Methodology for Placement of Analog and Mixed-signal Integrated Circuits," [pdf] Proc. of the 14th IEEE Int. Conf. on Electronics, Circuits and Systems (ICECS), Malta, pp. 770-773, Aug. 2008.

S. Rzepka, F. Krämer, O. Grassmé, J. Lienig "A Multilayer PCB Material Modeling Approach Based on Laminate Theory," [pdf] Proc. 9th Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE, Freiburg, pp. 234-243, April 2008.

T. Meister, J. Lienig, G. Thomke "Novel Pin Assignment Algorithms for Components with Very High Pin Counts," [pdf] Proc. Design, Automation and Test in Europe (DATE), Munich, pp. 837-842, March 2008.

J. Lienig, "Introduction to Electromigration-Aware Physical Design," Invited Talk, [pdf] Proc. of the Int. Symposium on Physical Design (ISPD'06), San Jose, CA, pp. 39-46, April 2006.

J. Lienig "Interconnect and Current Density Stress — An Introduction to Electromigration-Aware Design," Invited Talk, [pdf] Proc. of 2005 Int. Workshop on System Level Interconnect Prediction (SLIP), San Francisco, CA, pp. 81-88, April 2005.

J. Lienig, G. Jerke "Electromigration-Aware Physical Design of Integrated Circuits," Invited Tutorial, [pdf] Proc. of the 18th Int. Conference on VLSI Design, Kolkata, India, pp. 77-82, January 2005.

G. Jerke, J. Lienig, J. Scheible "Reliability-Driven Layout Decompaction for Electromigration Failure Avoidance in Complex Mixed-Signal IC Designs," [pdf, slides] Proc. of the Design Automation Conference (DAC'04), San Diego, CA, pp. 181-184, June 2004.

J. Lienig, G. Jerke "Current-Driven Wire Planning for Electromigration Avoidance in Analog Circuits," [pdf, ps, slides] Proc. of the 8th Asia and South Pacific Design Automation Conference (ASP-DAC), Kitakyusyu, Japan, pp. 783-788, 2003.

G. Jerke, J. Lienig "Hierarchical Current Density Verification for Electromigration Analysis in Arbitrarily Shaped Metallization Patterns of Analog Circuits," [pdf, ps, slides] Proc. Design, Automation and Test in Europe (DATE), Paris, pp. 464-469, 2002.

J. Lienig, G. Jerke, T. Adler "Electromigration Avoidance in Analog Circuits: Two Methodologies for Current Driven Routing," [pdf, ps, slides] Proc. of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC) and 15th International Conference on VLSI Design, Bangalore, India, pp. 372-378, 2002.

J. Lienig, G. Jerke, T. Adler "AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits," [pdf, ps] Proc. Design, Automation and Test in Europe (DATE), Munich, p. 819, 2001.

J. Lienig "Channel and Switchbox Routing with Minimized Crosstalk — A Parallel Genetic Algorithm Approach," [pdf, ps] Proc. of the 10th International Conference on VLSI Design, Hyderabad, India, pp. 27-31, 1997.

J. Lienig, J. P. Cohoon, "Genetic Algorithms Applied to the Physical Design of VLSI Circuits: A Survey," Parallel Problem Solving from Nature, Voigt, H.-M, Ebeling, W., Rechenberg, I., Schwefel, H.-P., eds., Lecture Notes in Computer Science, Vol. 1141, Berlin: Springer Verlag, pp. 839-848, 1996.

J. Lienig "A Parallel Genetic Algorithm for Two Detailed Routing Problems," Proc. of the Int. Symposium on Circuits and Systems, ISCAS-96, Atlanta, Georgia, pp. 508-511, 1996.

J. Lienig, K. Thulasiraman "GASBOR: A Genetic Algorithm for Switchbox Routing in Integrated Circuits," Proc. of the AI'94 Workshop on Evolutionary Computation, Armidale, pp. 199-212, 1994. Also in: Lecture Notes in Artificial Intelligence, Vol. 956, pp. 187-200, 1995.

J. Lienig, H. Brandt "An Evolutionary Algorithm for the Routing of Multi-Chip Modules," Parallel Problem Solving from Nature, Davidor, Y., Schwefel, H.-P., Männer, R., eds., Lecture Notes in Computer Science, Vol. 866, pp. 588-597, 1994.

J. Lienig, K. Thulasiraman "A New Genetic Algorithm for the Channel Routing Problem," Proc. of the 7th Int. Conference on VLSI Design, Calcutta, India, pp. 133-136, 1994.

J. Lienig, K. Thulasiraman, M. N. S. Swamy "Routing Algorithms for Multi-Chip Modules," [pdf] Proc. of the IEEE European Design Automation Conference (EDAC) , Hamburg, pp. 286-291, 1992.

R. Fischbach, J. Lienig, T. Meister "3D Physical Design: Challenges and Solutions," Tagungsband edaWorkshop 11, VDE Verlag, ISBN 978-3-8007-3353-8, pp. 39-44, May 2011.

J. Knechtel, J. Lienig "Eine Methodik zur Nutzung von klassischen IP-Blöcken in 3D-Schaltkreisen," Tagungsband edaWorkshop 11, VDE Verlag, ISBN 978-3-8007-3353-8, pp. 45-50, May 2011.

A. Krinke, J. Lienig "Neuartige Entwurfsmethodik zur Berücksichtigung des IR-Drop bei der Power-Verdrahtung analoger Schaltungen," [pdf] Tagungsband Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2011), Fraunhofer Verlag, ISBN 978-3-8396-0259-1, pp. 42-47, May 2011.

M. Thiele, J. Lienig "Elektromigrationserscheinungen in zukünftigen digitalen Schaltungen," Tagungsband Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2011), Fraunhofer Verlag, ISBN 978-3-8396-0259-1, pp. 30-35, May 2011.

J. Hertwig, M. Thiele, H. Neubert, J. Lienig "Modellierung CNT-basierter thermischer Vias für den effektiven Wärmetransport," [pdf] Tagungsband Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2011), Fraunhofer Verlag, ISBN 978-3-8396-0259-1, pp. 24-29, May 2011.

J. Hertwig, H. Neubert, J. Lienig "Ein Ansatz zur Modellierung CNT-basierter thermischer Vias für den effektiven Wärmetransport in elektronischen Schaltkreisen," [pdf] Tagungsband Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2010), Fraunhofer Verlag, ISBN 978-3-8396-0126-6, pp. 43-48, May 2010.

R. Fischbach, J. Lienig, T. Meister "Herausforderungen bei der Automatisierung des Layoutentwurfs bei dreidimensionalen heterogenen Systemen," Tagungsband Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2010), Fraunhofer Verlag, ISBN 978-3-8396-0126-6, pp. 37-42, May 2010.

R. Fischbach, J. Lienig, J. Hertwig "Modern 3D Data Structures: Classification, Comparison and Solution Space Investigation," Tagungsband edaWorkshop 10, VDE Verlag, ISBN 978-3-8007-3252-4, pp. 41-46, May 2010.

T. Meister, J. Lienig "Routability Prediction for Three-Dimensional Circuits," Tagungsband edaWorkshop 10, VDE Verlag, ISBN 978-3-8007-3252-4, pp. 29-34, May 2010.

T. Meister, J. Lienig "Neue Herausforderungen an die Verdrahtungsvorhersage beim 3D-Layoutentwurf," [pdf] GMM-Fachbericht 61, Zuverlässigkeit und Entwurf, VDE Verlag, pp. 99-106, Sept. 2009.

R. Fischbach, J. Lienig "3D-Integration und 3D-Datenstrukturen — Eine Übersicht," [pdf] Tagungsband edaWorkshop 09, VDE Verlag, pp. 7-12, May 2009.

J. Lienig "Elektromigration und deren Berücksichtigung beim Layoutentwurf," [pdf] Tagungsband Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS 2008), ISBN 3-9810287-2-4, pp. 13-14, May 2008.

A. Nassaj, J. Lienig, G. Jerke, J. Freuer "Constraint-geführte Floorplan-Generierung von integrierten Analog- und Mixed-Signal-Schaltungen," [pdf] GMM-Fachbericht ANALOG '08, Siegen, pp. 159-164, April 2008.

T. Meister, J. Lienig, G. Thomke "Pinzuordnungs-Algorithmen für hochkomplexe Area-Array-Komponenten," [pdf] GMM-Fachbericht ANALOG '08, Siegen, pp. 177-182, April 2008.